1. Field of the Invention
The present invention relates to a data reading circuit, and particularly relates to a data reading circuit which adjusts according to a delay state of the data reading clock signal of the memory.
2. Description of the Prior Art
In modern electronics, a memory is used for storing various kinds of data, where a data reading clock signal is used for reading the data in the memory. The elements and connection lines of an electronic apparatus become complicated as related techniques improve, however, potentially resulting in delay of the data reading clock signal. Such an error may be caused by the delay when reading data through a pad. If the memory is used for ASICs (Application Specific Integrated Circuit), such a problem becomes even more serious. Because each ASIC has its different characteristics, the system may be unstable and a design error will occur if the problem of a delayed data read clock signal is not solved.
Many inventions and related techniques are developed for solving this problem. FIG. 1 discloses a prior art data reading circuit, which is disclosed in U.S. Pat. No. 6,529,424. As shown in FIG. 1, a memory 101 is used for storing data, and an ASIC 103 provides a data reading clock signal to the memory 101 for data reading. The ASIC 103 further includes a test port 105 to send the test signal TS to the memory 101, and a feedback port 107 to receive a test signal TS from the memory 101. The delay for a signal transmitting from the ASIC 103 to the memory 101 is simulated, and the system can be adjusted according to the delay. A circuit of such would need an extra test port 105, an extra feedback port 107 and corresponding lines, i.e. with additional cost. Moreover, an extra step for simulating delay is also necessary, and the loading of the system thereby increases. By the way, a synchronization procedure would be required for the input data.
Therefore, a new invention is desired for solving the above-mentioned problems.